(1) Field of the Invention
The invention relates to a Class-D Power Amplifier, and more particularly, to a Class-D Power Amplifier having a pulse coded digital input signal and typically using an H-Bridge to drive an output load, like a loudspeaker.
(2) Description of the Prior Art
Class-AB amplifiers are notoriously inefficient and Class-D amplifiers overcome this shortfall. With Class D amplifiers, the output is made to switch between the two output levels at a very high frequency—substantially higher than the highest audible frequency, which is done by feeding high-frequency pulses to the power amplification stage. The pulse-width ratio or the pulse density of the driving signal can be varied to make the averaged (filtered) output signal follow the (amplified) input signal very closely; such amplifier is referred to as pulse width modulated (PWM) or as pulse density modulated (PDM). The filtered output voltage at the load represents the input signal correct as long as the supply voltage is perfectly constant, which however is not true in real life.
To overcome the problem of supply voltage fluctuations, a specific technique might be implemented to always keep the time-voltage area of each pulse constant. However due to such pulse time correction, the center of each pulse will then no longer be repeated with the intended clock rate and the resulting jitter introduces noise and spuriouses.
Another area, where the center of each pulse will not be repeated with the intended clock rate, is an amplifier, where the output pulse width may have one of several discrete values to provide a multi-level output system.
Specifically, Patent Disclosure DS02-012, “Linearization of a PDM Class-D Amplifier”, to which this disclosure relates, describes the invention to such Pulse Area Correction Mechanism. Also, Patent Disclosure DS02-014, “Multi-level Class D amplifier by means of 3 physical levels.” to which this disclosure relates, describes the invention of an amplifier, where the output pulse width may have one of several discrete values to provide a multi-level output system
FIG. 1 prior art shows a schematic block diagram of a PDM Class-D Amplifier with a Pulse Area Correction Mechanism inserted into the signal path. It typically comprises a Sigma Delta Modulator converter, to generate the driving pulses and it comprises a power output stage, which is typically an H-Bridge.
FIG. 2 prior art shows a simplified diagram of an H-Bridge.
U.S. Pat. No. (5,949,282 to Nguyen, Huey, Takagishi, Hideto) describes circuit for, first, generating an accurate reproduction of the output of a Class D amplifier for error-correction purposes, and then, second, comparing the reference signal to the original signal input to the amplifier for error-correcting purposes.
U.S. Pat. No. (5,847,602 to Su, David) shows a delta-modulated magnitude amplifier which is used to amplify the magnitude component of an RF power amplifier that employs envelope elimination and restoration. The delta-modulated amplifier introduces a smaller amount of non-linearity than traditional approaches, which are based upon pulse-width modulation. The disclosed technique can be implemented using switched-capacitor circuits in a standard MOS technology with only two external components, i.e., an inductor and a capacitor. Thus, the disclosed technique allows the implementation of an efficient and yet linear RF power amplifier using low-cost MOS technology.
U.S. Pat. No. (5,974,089 Tripathi, et al) describes an oversampled, noise shaping signal processor having at least one integrator stage in a feedback loop. A sampling stage in the feedback loop is coupled to the at least one integrator stage. The sampling stage samples an analog signal at a sample frequency. Qualification logic coupled to the sampling stage receives a pulse waveform therefrom, and ensures that signal transitions in the pulse waveform occur more than a first time period apart and that the waveform can therefore be handled by, for example, a power switching device. A switching stage in the feedback loop is coupled to the qualification logic. The signal processor has a feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop.